Avago Technologies LSI53C876E User Manual
Page 172
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Registers
•
Offset Overflow – the other SCSI device sends a
SREQ/ or SACK/ pulse with data which exceeds the
maximum synchronous offset defined by the
register.
•
A phase change occurs with an outstanding
synchronous offset when the LSI53C876 SCSI
function is operating as an initiator.
•
Residual data in the synchronous data FIFO – a
transfer other than synchronous data receive is
started with data left in the synchronous data FIFO.
UDC
Unexpected Disconnect
2
This bit is set when the LSI53C876 SCSI function is
operating in initiator mode and the target device
unexpectedly disconnects from the SCSI bus. This bit is
only valid when the LSI53C876 SCSI function operates in
the initiator mode. When the SCSI function operates in
low level mode, any disconnect causes an interrupt, even
a valid SCSI disconnect. This bit is also set if a selection
time-out occurs (it may occur before, at the same time, or
stacked after the STO interrupt, since this is not
considered an expected disconnect).
RST
SCSI RST/ Received
1
This bit is set when the LSI53C876 SCSI function detects
an active SRST/ signal, whether the reset is generated
external to the chip or caused by the Assert SRST/ bit in
the
register. This SCSI
reset detection logic is edge-sensitive, so that multiple
interrupts are not generated for a single assertion of the
SRST/ signal.
PAR
Parity Error
0
This bit is set when the LSI53C876 SCSI function detects
a parity error while receiving SCSI data. The Enable
Parity Checking bit (bit 3 in the
register) must be set for this bit to become
active. The LSI53C876 SCSI function always generates
parity when sending SCSI data.