Avago Technologies LSI53C876E - Manual (Page 25)

PCI Functional Description 2-3
2.1 PCI Functional Description
The LSI53C876 implements two PCI-to-Wide Ultra SCSI controllers in a
single package. This configuration presents only one load to the PCI bus
and uses one REQ/ - GNT/ pair to arbitrate for PCI bus mastership.
However, separate interrupt signals are generated for SCSI Function A
and SCSI Function B.
2.1.1 PCI Addressing
There are three physical PCI-defined address spaces:
•
Configuration Space
•
I/O Space
•
Memory Space
2.1.1.1 Configuration Space
Two independent sets of configuration space registers are defined, one
set for each SCSI function. The Configuration registers are accessible
only by system BIOS during PCI configuration cycles. The configuration
space is a contiguous 256 x 8-bit set of addresses. Decoding C_BE/[3:0]
determines if a PCI cycle is intended to access configuration register
space. The IDSEL bus signal is a “chip select” that allows access to the
configuration register space only. A configuration read/write cycle without
IDSEL is ignored. The eight lower order address bits AD[7:0], are used
to select a specific 8-bit register. Since the LSI53C876 is a PCI
multifunction device, AD[10:8] decodes either SCSI Function A
Configuration register (AD [10:8] = 000 binary) or SCSI Function B
Configuration register (AD [10:8] = 001 binary). The host processor uses
this configuration space to initialize the LSI53C876.
At initialization time, each PCI device is assigned a base address for
memory accesses and I/O accesses. In the case of the LSI53C876, the
upper 24 bits of the address are selected. On every access, the
LSI53C876 compares its assigned base addresses with the value on the
Address/Data bus during the PCI address phase. If the upper 24 bits
match, the access is for the LSI53C876 and the low-order eight bits
define the register being accessed. A decode of C_BE/[3:0] determines
which registers and what type of access is to be performed.