Base address register one, Memory), Base address register two (memory) – Avago Technologies LSI53C876E User Manual
Page 104: Base address register one (memory), 0x14, 0x18, Reserved, Base address reg, Ister one (memory), Base address register two
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Registers
Register: 0x14
Base Address Register One (Memory)
Read/Write
BAR1
Base Address Register One
[31:0]
This register has bit zero hardwired to zero. For detailed
information on the operation of this register, refer to the
PCI specification. This
register maps SCSI operating registers into
memory space.
Register: 0x18
Base Address Register Two (Memory)
Read/Write
BAR2
Base Address Register Two
[31:0]
This register has bit zero hardwired to zero. The other
bits are used to map the 4 Kbyte SCRIPTS RAM into
memory space. This register is enabled only if the
internal SCRIPTS RAM is enabled. The internal
SCRIPTS RAM is disabled by connecting a 4.7 k
Ω
resistor between MAD5 and ground, which is sensed
immediately after a chip reset. SCRIPTS RAM is also
disabled by setting the Enable Memory Space bit to zero
in the SCSI PCI Configuration
register, bit 1.
If MAD5 is left unconnected, an internal pull-up enables
the SCRIPTS RAM and this Base Address register.
If enabled, as with all Base Address registers, initialize
this Base Address register to a value that does not
conflict with other memory resources. Otherwise,
memory conflicts may occur.
For detailed information on the operation of this register,
refer to the PCI specification.
31
0
BAR1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
31
0
BAR2
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0