3 opcode fetch burst capability – Avago Technologies LSI53C876E User Manual
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SCSI Functional Description
2-15
chip is prefetching SCRIPTS instructions, the PCI
register value does not have any effect and the Read Line, Read
Multiple, and Write and Invalidate commands are not used.
Note:
This feature is only useful if fetching SCRIPTS instructions
from main memory. Due to the short access time of
SCRIPTS RAM, prefetching is not necessary when fetching
instructions from this memory.
The LSI53C876 may flush the contents of the prefetch unit under certain
conditions, listed below, to ensure that the chip always operates from the
most current version of the SCRIPTS instruction. When one of these
conditions apply, the contents of the prefetch unit are automatically
flushed.
•
On every Memory Move instruction. The Memory Move instruction
often places modified code directly into memory. To make sure that
the chip executes all recent modifications, the prefetch unit flushes
its contents and loads the modified code every time a instruction is
issued. To avoid inadvertently flushing the prefetch unit contents, use
the No Flush option for all Memory Move operations that do not
modify code within the next 8 Dwords. For more information on this
instruction, refer to
Chapter 5, “SCSI SCRIPTS Instruction Set.”
•
On every Store instruction. The Store instruction may also be used
to place modified code directly into memory. To avoid inadvertently
flushing the prefetch unit contents use the No Flush option for all
Store operations that do not modify code within the next 8 Dwords.
•
On every write to the
register.
•
On all Transfer Control instructions when the transfer conditions are
met. This is necessary because the next instruction to execute is not
the sequential next instruction in the prefetch unit.
•
When the Prefetch Flush bit (
register
,
bit 6)
is set. The unit flushes whenever this bit is set. The bit is
self-clearing.
2.2.2.3 OpCode Fetch Burst Capability
Setting the Burst OpCode Fetch Enable bit (bit 1) in the
register (0x38) causes the LSI53C876 to burst in the first two
Dwords of all instruction fetches. If the instruction is a Memory-to-