Avago Technologies LSI53C876E User Manual
Page 168
4-74
Registers
RSL
Reselected
4
Setting this bit allows the LSI53C876 to generate an
interrupt when the LSI53C876 has been reselected by
another SCSI device. Set the Enable Response to
Reselection bit in the
register for
this to occur.
SGE
SCSI Gross Error
3
Setting this bit allows the LSI53C876 to generate an
interrupt when a SCSI gross error occurs. The following
conditions are considered SCSI Gross Errors:
•
Data underflow – reading the SCSI FIFO when no
data is present.
•
Data overflow – writing the SCSI FIFO while it is full.
•
Offset underflow – receiving a SACK/ pulse in target
mode before the corresponding SREQ/ is sent.
•
Offset overflow – receiving an SREQ/ pulse in the
initiator mode, and exceeding the maximum offset
(defined by the MO[3:0] bits in the
register).
•
A phase change in the initiator mode, with an
outstanding SREQ/SACK offset.
•
Residual data in SCSI FIFO – starting a transfer other
than synchronous data receive with data left in the
SCSI synchronous receive FIFO.
UDC
Unexpected Disconnect
2
Setting this bit allows the LSI53C876 to generate an
interrupt when an unexpected disconnect occurs. This
condition only occurs in the initiator mode. It happens
when the target to which the LSI53C876 is connected
disconnects from the SCSI bus unexpectedly. See the
SCSI Disconnect Unexpected bit in the
register for more information on expected
versus unexpected disconnects. Any disconnect in low
level mode causes this condition.