Avago Technologies LSI53C876E User Manual
Page 98
4-4
Registers
[15:9]
SE
SERR/ Enable
8
This bit enables the SERR/ driver. SERR/ is disabled
when this bit is cleared. The default value of this bit is
zero. This bit and bit 6 must be set to report address
parity errors. In the LSI53C876E, this bit is suppressed in
Power State D2.
R
Reserved
7
EPER
Enable Parity Error Response
6
This bit allows a SCSI function of the LSI53C876E to
detect parity errors on the PCI bus and report these
errors to the system. Only data parity checking is enabled
and disabled with this bit. The LSI53C876 always
generates parity for the PCI bus. In the LSI53C876E, this
bit is suppressed in Power State D2.
R
Reserved
5
WIE
Write and Invalidate Enable
4
This bit allows a SCSI function of the LSI53C876 to
generate write and invalidate commands on the PCI bus.
The WRIE bit in the
register
must also be set for the SCSI function to generate Write
and Invalidate commands.
R
Reserved
3
EBM
Enable Bus Mastering
2
This bit controls the ability of a SCSI function to act as a
master on the PCI bus. A value of zero disables this
device from generating PCI bus master accesses. A
value of one allows the SCSI function to behave as a bus
master. The SCSI function must be a bus master in order
to fetch SCRIPTS instructions and transfer data. In the
LSI53C876E, this bit is suppressed in Power State D2.
EMS
Enable Memory Space
1
This bit controls the ability of a SCSI function to respond
to Memory space accesses. A value of zero disables the
device response. A value of one allows a SCSI function
of the LSI53C876 to respond to Memory Space accesses
at the address range specified by the
and