Avago Technologies LSI53C876E - Manual (Page 96)

4-2 Registers
Table 4.1 PCI to SCSI Configuration Register Map
31 16 15 0
Device ID Vendor ID 0x00
Status Command 0x04
Class Code Revision ID 0x08
Not Supported Header Type Latency Timer Cache Line Size 0x0C
Base Address Register Zero (I/O) SCSI Operating Registers 0x10
Base Address Register One (Memory) bits [31:0] SCSI Operating Registers 0x14
Base Address Register Two (Memory) 0x18
Not Supported 0x1C
Not Supported 0x20
Not Supported 0x24
Reserved 0x28
Subsystem ID Subsystem Vendor ID 0x2C
Expansion ROM Base Address 0x30
Reserved Capabilities Pointer 0x34
Reserved 0x38
Max_Lat Min_Gnt Interrupt Pin 1
1. Each SCSI function contains the same register set with identical default values. One exception is
the Interrupt Pin register.
Note: Shaded areas are reserved or represent the LSI53C876E capabilities.
Interrupt Line 0x3C
Power Management Capabilities Next Item Pointer Capability ID 0x40
Data PMCSR BSE Power Management Control/Status 0x44