Avago Technologies LSI53C876E User Manual
Page 161
SCSI Registers
4-67
during normal operation. The fairness delay is not
inserted during PCI retry cycles. This gives the CPU and
other bus master devices the opportunity to access the
PCI bus between bursts.
SIOM
Source I/O Memory Enable
5
This bit is defined as an I/O Memory Enable bit for the
source address of a Memory Move or Block Move
Command. If this bit is set, then the source address is in
I/O space; and if cleared, then the source address is in
memory space.
This function is useful for register-to-memory operations
using the Memory Move instruction when a LSI53C876
SCSI function is I/O mapped. Bits 4 and 5 of the
register determine the configuration
status of the LSI53C876 SCSI function.
DIOM
Destination I/O Memory Enable
4
This bit is defined as an I/O Memory Enable bit for the
destination address of a Memory Move or Block Move
Command. If this bit is set, then the destination address
is in I/O space; and if cleared, then the destination
address is in memory space.
This function is useful for memory-to-register operations
using the Memory Move instruction when a LSI53C876
SCSI function is I/O mapped. Bits 4 and 5 of the
register determine the configuration
status of the LSI53C876 SCSI function.
BL2
(CTEST5 bit 2)
BL1
BL0
Burst Length
0
0
0
2-transfer burst
0
0
1
4-transfer burst
0
1
0
8-transfer burst
0
1
1
16-transfer burst
1
0
0
32-transfer burst
1
1
0
1
64-transfer burst
1
1
1
0
128-transfer burst
1
1
1
1
Reserved
1. Only valid if the FIFO size is set to 536 bytes.