8 synchronous operation, 1 determining the data transfer rate, Synchronous operation – Avago Technologies LSI53C876E User Manual
Page 52
2-30
Functional Description
2.2.8 Synchronous Operation
The LSI53C876 can transfer synchronous SCSI data in both initiator and
target modes. The
register controls both the
synchronous offset and the transfer period. It may be loaded by the CPU
before SCRIPTS execution begins, from within SCRIPTS using a Table
Indirect I/O instruction, or with a Read-Modify-Write instruction.
The LSI53C876 can receive data from the SCSI bus at a synchronous
transfer period as short as 50 ns, regardless of the transfer period used
to send data. The chip can receive data at one-fourth of the divided
SCLK frequency. Depending on the SCLK frequency, the negotiated
transfer period, and the synchronous clock divider, the chip can send
synchronous data at intervals as short as 50 ns for Ultra SCSI, 100 ns
for Fast SCSI, and 200 ns for SCSI-1.
2.2.8.1 Determining the Data Transfer Rate
Synchronous data transfer rates are controlled by bits in two different
registers of the LSI53C876. Following is a brief description of the bits.
illustrates the clock division factors used in each register, and
the role of the register bits in determining the transfer rate.
2.2.8.2
Register, Bits [6:4] (SCF[2:0])
The SCF[2:0] bits select the factor by which the frequency of SCLK is
divided before being presented to the synchronous SCSI control logic.
The output from this divider controls the rate at which data can be
received; this rate must not exceed 80 MHz. The receive rate is
one-fourth of the divider output.
2.2.8.3
Register, Bits [2:0] (CCF[2:0]
The CCF[2:0] bits select the factor by which the frequency of SCLK is
divided before being presented to the asynchronous SCSI controller
logic. This divider must be set according to the input clock frequency in
the table.
2.2.8.4
Register, Bits [7:5] (TP[2:0])
The TP[2:0] bits determine the SCSI synchronous transfer period when
sending synchronous SCSI data in either initiator or target mode.