1 internal scripts ram, 2 prefetching scripts instructions – Avago Technologies LSI53C876E User Manual
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Functional Description
without sacrificing I/O performance. SCSI SCRIPTS are hardware
independent, so they can be used interchangeably on any host or CPU
system bus.
2.2.2.1 Internal SCRIPTS RAM
The LSI53C876 has 4 Kbytes (1024 x 32 bits) of internal, general
purpose RAM. The RAM is designed for SCRIPTS program storage, but
is not limited to this type of information. When the chip fetches SCRIPTS
instructions or Table Indirect information from the internal RAM, these
fetches remain internal to the chip and do not use the PCI bus. Other
types of access to the RAM by the chip use the PCI bus, as if they were
external accesses. The MAD5 pin disables the 4 K internal RAM. To
disable the internal RAM, connect a 4.7 k
Ω
resistor between the MAD5
pin and V
SS
(ground). The SCRIPTS RAM powers up enabled by default.
The RAM can be relocated by the PCI system BIOS anywhere in 32-bit
address space. The
Base Address Register Two (Memory)
register in
PCI configuration space contains the base address of the internal RAM.
This register is similar to the ROM Base Address register in PCI
configuration space. To simplify loading of the SCRIPTS instructions, the
base address of the RAM appears in the
register when bit 3 of the
register
is set. The RAM is byte accessible from the PCI bus and is visible to any
bus mastering device on the bus. External accesses to the RAM (by the
CPU) follow the same timing sequence as a standard slave register
access, except that the required target wait-states drop from 5 to 3.
A complete set of development tools is available for writing custom
drivers with SCSI SCRIPTS. For more information on the SCSI SCRIPTS
instructions supported by the LSI53C876, see
2.2.2.2 Prefetching SCRIPTS Instructions
When enabled by setting the Prefetch Enable bit (bit 5) in the
register, the prefetch logic in the LSI53C876 fetches
8 Dwords of instructions. The prefetch logic automatically determines the
maximum burst size that it can perform based on the burst length as
determined by the values in the
register. If the unit
cannot perform bursts of at least four Dwords, it disables itself. While the