Register: 0x4c – Avago Technologies LSI53C876E User Manual
Page 181
SCSI Registers
4-87
and
registers. However, the chip can arbitrate with
only one ID value in the
register.
Register: 0x4C
SCSI Test Zero (STEST0)
Read Only
SSAID[3:0]
SCSI Selected As ID
[7:4]
These bits contain the encoded value of the SCSI ID that
the LSI53C876 SCSI function is selected or reselected as
during a SCSI selection or reselection phase. These bits
are read only and contain the encoded value of 0–15
possible IDs that could be used to select the LSI53C876
SCSI function. During a SCSI selection or reselection
phase when a valid ID is put on the bus, and the
LSI53C876 SCSI function responds to that ID, the
“selected as” ID is written into these bits. These bits are
used with the RESPID registers to allow response to
multiple IDs on the bus.
SLT
Selection Response Logic Test
3
This bit is set when the LSI53C876 SCSI function is
ready to be selected or reselected. This does not take
into account the bus settle delay of 400 ns. This bit is
used for functional test and fault purposes.
ART
Arbitration Priority Encoder Test
2
This bit is always set when the LSI53C876 SCSI function
exhibits the highest priority ID asserted on the SCSI bus
during arbitration. It is primarily used for chip level testing,
but it may be used during low level mode operation to
determine if the LSI53C876 SCSI function won
arbitration.
SOZ
SCSI Synchronous Offset Zero
1
This bit indicates that the current synchronous SREQ/,
SACK/ offset is zero. This bit is not latched and may
change at any time. It is used in low level synchronous
SCSI operations. When this bit is set, the LSI53C876
7
4
3
2
1
0
SSAID[3:0]
SLT
ART
SOZ
SOM
0
0
0
0
0
x
1
1