Avago Technologies LSI53C876E - Manual (Page 248)

6-16 Electrical Characteristics
•
Read Cycle, Normal/Fast Memory (
≥
128 Kbyte), Multiple Byte
Access
•
Write Cycle, Normal/Fast Memory (
≥
128 Kbyte), Multiple Byte
Access
•
Read Cycle, Slow Memory (
≥
128 Kbytes)
•
Write Cycle, Slow Memory (
≥
128 Kbytes)
•
Read Cycle, 16 Kbytes ROM
•
Write Cycle, 16 Kbytes ROM
6.4.1.1 3.3 V PCI Timings
Note: When a 3.3 V source is applied to the V
DD
-I pins of the
LSI53C876, some of the PCI timing data in Table 6.24
through Table 6.35 will change. The 3.3 V PCI timing data
is listed in Table 6.24 .
Table 6.24 3.3 V PCI Timing
Symbol Parameter Min Max Unit
t
2
Shared signal input hold time 1 – ns
t
3
CLK to shared signal output valid – 12 ns