Avago Technologies LSI53C876E - Manual (Page 147)

SCSI Registers 4-53
DIP DMA Interrupt Pending 0
This status bit is set when an interrupt condition is
detected in the DMA portion of the LSI53C876 SCSI
function. The following conditions cause a DMA interrupt
to occur:
•
A PCI parity error is detected
•
A bus fault is detected
•
An abort condition is detected
•
A SCRIPTS instruction is executed in single step
mode
•
A SCRIPTS interrupt instruction is executed
•
An illegal instruction is detected.
To determine exactly which condition(s) caused the
interrupt, read the
DMA Status (DSTAT) register
Register: 0x18
Chip Test Zero (CTEST0)
Read/Write
R Reserved [7:3]
AP[2:0] Arbitration Priority [2:0]
These bits are the priority used for gaining access to the
PCI bus through the internal arbiter in the LSI53C876
SCSI function. Valid arbitration priority values are 0
(lowest priority) through 7 (highest priority).
7 3 2 0
R AP[2:0]
0 x x x x 1 1 1