Avago Technologies LSI53C876E User Manual
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Functional Description
Line bit (
register, bit 3) is modified to more
resemble the Write and Invalidate mode in terms of conditions that must
be met before a Read Line command is issued. However, the Read Line
option operates exactly like the previous LSI53C8XX chips when cache
mode is disabled by a CLSE bit reset or when certain conditions exist in
the chip (explained below).
If cache mode is disabled, Read Line commands are issued on every
read data transfer, except opcode fetches, as in previous LSI53C8XX
chips.
If cache mode is enabled, a Read Line command is issued on all read
cycles, except opcode fetches, when the following conditions are met:
•
The CLSE (Cache Line Size Enable, bit 7,
register) and ERL (Enable Read Line, bit 3,
register) bits are set.
•
The
register for each function must contain a legal
burst size value (2, 4, 8, 16, 32, 64, or 128) and that value is less
than or equal to the
burst size.
•
The number of bytes to be transferred at the time a cache boundary
is reached is equal to or greater than the
burst
size.
•
The chip is aligned to a cache line boundary.
When these conditions are met, the chip issues a Read Line command
instead of a Memory Read during all PCI read cycles. Otherwise, it
issues a normal Memory Read command.
Read Multiple with Read Line Enabled – When both the Read
Multiple and Read Line modes are enabled, the Read Line command is
not issued if the above conditions are met. Instead, a Read Multiple
command is issued, even though the conditions for Read Line are met.
If the Read Multiple mode is enabled and the Read Line mode is
disabled, Read Multiple commands are issued if the Read Multiple
conditions are met.