Avago Technologies LSI53C876E - Manual (Page 111)

PCI Configuration Registers 4-17
Register: 0x41
Next Item Pointer
Read Only
NIP Next_Item_Ptr [7:0]
This register describes the location of the next item in the
function’s capability list. This register applies only to the
LSI53C876E, which sets this register to a value of 0x00,
indicating that power management is the last capability in
the linked list of extended capabilities.
Register: 0x42
Power Management Capabilities
Read Only
This register applies to the LSI53C876E only and indicates the power
management capabilities.
PMES[4:0] PME Support [15:11]
This field is always set to 00000b because the
LSI53C876E does not provide a PME signal.
D2S D2 Support 10
The LSI53C876E sets this bit to indicate that it supports
the D2 power management state.
D1S D1 Support 9
The LSI53C876E sets this bit to indicate that it supports
the D1 power management state.
R Reserved [8:6]
DSI Device Specific Initialization 5
This bit is set to 0 to indicate that the LSI53C876E
requires no special initiation before the generic class
device driver is able to use it.
7 0
NIP
0 0 0 0 0 0 0 0
15 11 10 9 8 6 5 4 3 2 0
PMES[4:0] D2S D1S R DSI APS PMEC VER[2:0]
0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1