Scsi status zero (sstat0), Scsi status zero, Sstat0) – Avago Technologies LSI53C876E User Manual
Page 138: Register: 0x0d
4-44
Registers
•
A Load/Store instruction is issued with the memory
address mapped to the operating registers of the chip,
not including ROM or RAM.
•
A Load/Store instruction is issued when the register
address is not aligned with the memory address.
•
A Load/Store instruction is issued with bit 5 in the
register cleared or bits 3 or
2 set.
•
A Load/Store instruction when the count value in the
register is not set at 1 to 4.
•
A Load/Store instruction attempts to cross a Dword
boundary.
•
A Memory Move instruction is executed with one of
the reserved bits in the
register set.
•
A Memory Move instruction is executed with the
source and destination addresses not aligned.
Register: 0x0D
SCSI Status Zero (SSTAT0)
Read Only
ILF
SIDL Least Significant Byte Full
7
This bit is set when the least significant byte in the
register contains data. Data is
transferred from the SCSI bus to the SIDL register before
being sent to the DMA FIFO and then to the host bus.
The SIDL register contains SCSI data received
asynchronously. Synchronous data received does not
flow through this register.
ORF
SODR Least Significant Byte Full
6
This bit is set when the least significant byte in the SCSI
Output Data Register (SODR, a hidden buffer register
which is not accessible) contains data. The SCSI logic
uses the SODR as a second storage register when
7
6
5
4
3
2
1
0
ILF
ORF
OLF
AIP
LOA
WOA
RST/
SDP0/
0
0
0
0
0
0
0
0