Scsi control three (scntl3), Register: 0x03 – Avago Technologies LSI53C876E User Manual
Page 125
SCSI Registers
4-31
Register: 0x03
SCSI Control Three (SCNTL3)
Read/Write
USE
Ultra SCSI Enable
7
Setting this bit enables Ultra SCSI synchronous transfers.
The default value of this bit is 0. Set this bit only when
the transfer rate exceeds 10 megatransfers/s.
When this bit is set, the signal filtering period for SREQ/
and SACK/ automatically changes to 15 ns, regardless of
the value of the Extend REQ/ACK Filtering bit in the
register.
SCF[2:0]
Synchronous Clock Conversion Factor
[6:4]
These bits select a factor by which the frequency of
SCLK is divided before being presented to the
synchronous SCSI control logic. Write these to the same
value as the Clock Conversion Factor bits below unless
fast SCSI operation is desired. See the
register description for examples of how the
SCF bits are used to calculate synchronous transfer
periods. See the table under the description of bits [7:5]
of the
register for the valid
combinations.
Note;
For additional information on how the synchronous transfer
rate is determined, refer to
Chapter 2, “Functional Descrip-
EWS
Enable Wide SCSI
3
When this bit is clear, all information transfer phases are
assumed to be eight bits, transmitted on SD[7:0]/, SDP0/.
When this bit is asserted, data transfers are done 16 bits
at a time, with the least significant byte on SD[7:0]/, SDP/
and the most significant byte on SD[15:8]/, SDP1/.
Command, Status, and Message phases are not affected
by this bit.
7
6
4
3
2
0
USE
SCF[2:0]
EWS
CCF[2:0]
0
0
0
0
0
0
0
0