4 load/store instructions, 3 jtag boundary scan testing, Jtag boundary scan testing – Avago Technologies LSI53C876E User Manual
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Functional Description
Memory Move, the third Dword is accessed in a separate ownership. If
the instruction is an indirect type, the additional Dword is accessed in a
subsequent bus ownership. If the instruction is a Table Indirect Block
Move, the chip uses two accesses to obtain the four Dwords required, in
two bursts of two Dwords each.
Note:
This feature is only useful if prefetching is disabled and
SCRIPTS instructions are fetched from main memory. Due
to the short access time of SCRIPTS RAM, burst opcode
fetching is not necessary when fetching instructions from
this memory.
2.2.2.4 Load/Store Instructions
The LSI53C876 supports the Load and Store instruction type, which
simplifies the movement of data between memory and the internal chip
registers. It also enables the chip to transfer bytes to addresses relative
to the
register. For more information on
the Load and Store instructions, refer to
2.2.3 JTAG Boundary Scan Testing
The LSI53C876 includes support for JTAG boundary scan testing in
accordance with the IEEE 1149.1 specification with one exception, which
is explained in this section. This device accepts all required boundary
scan instructions including the optional CLAMP, HIGH-Z, and IDCODE
instructions.
The LSI53C876 uses an 8-bit instruction register to support all boundary
scan instructions. The data registers included in the device are the
Boundary Data register, the IDCODE register, and the Bypass register.
This device can handle a 10 MHz TCK frequency for TDO and TDI.
Due to design constraints, the RST/ pin (system reset) always 3-states
the SCSI pins when it is asserted. Boundary scan logic does not control
this action, and this is not compliant with the specification. There are two
solutions that resolve this issue: