Avago Technologies LSI53C876E User Manual
Page 202
5-12
SCSI SCRIPTS Instruction Set
5. If the SCSI phase bits do not match the value stored
in the
register, the
LSI53C876 generates a phase mismatch interrupt
and the instruction is not executed.
6. During a Message-Out phase, after the LSI53C876
has performed a select with Attention (or SATN/ is
manually asserted with a Set ATN instruction), the
LSI53C876 deasserts SATN/ during the final
SREQ/SACK/ handshake.
7. When the LSI53C876 is performing a block move for
Message-In phase, it does not deassert the SACK/
signal for the last SREQ/SACK/ handshake. Clear the
SACK/ signal using the Clear SACK I/O instruction.
SCSIP[2:0]
SCSI Phase
[26:24]
This 3-bit field defines the desired SCSI information
transfer phase. When the LSI53C876 operates in Initiator
mode, these bits are compared with the latched SCSI
phase bits in the
register.
When the LSI53C876 operates in Target mode, it asserts
the phase defined in this field. The following table
describes the possible combinations and the
corresponding SCSI phase.
TC
Transfer Counter
[23:0]
This 24-bit field specifies the number of data bytes to
move between the LSI53C876 and system memory. The
field is stored in the
register.
When the LSI53C876 transfers data to/from memory, the
DBC register is decremented by the number of bytes
MSG C_D
I_O
SCSI Phase
0
0
0
Data-Out
0
0
1
Data-In
0
1
0
Command
0
1
1
Status
1
0
0
Reserved-Out
1
0
1
Reserved-In
1
1
0
Message-Out
1
1
1
Message-In