Avago Technologies LSI53C876E - Manual (Page 170)

4-76 Registers
GEN General Purpose Timer Expired 1
Setting this bit allows the LSI53C876 to generate an
interrupt when the general purpose timer has expired.
The time measured is the time between enabling and
disabling of the timer. See the description of the
SCSI
Timer One (STIME1) register, bits [3:0], for more
information on the general purpose timer.
HTH Handshake-to-Handshake Timer Expired 0
Setting this bit allows the LSI53C876 to generate an
interrupt when the handshake-to-handshake timer has
expired. The time measured is the SCSI Request-to-
Request (target) or Acknowledge-to-Acknowledge
(initiator) period. See the description of the
SCSI Timer
Zero (STIME0) register, bits [7:4], for more information on
the handshake-to-handshake timer.
Register: 0x42
SCSI Interrupt Status Zero (SIST0)
Read Only
Reading the SIST0 register returns the status of the various interrupt
conditions, whether they are enabled in the
SCSI Interrupt Enable Zero
(SIEN0) register or not. Each bit set indicates occurrence of the
corresponding condition. Reading the SIST0 clears the interrupt status.
Reading this register clears any bits that are set at the time the register
is read, but does not necessarily clear the register because additional
interrupts may be pending (the LSI53C876 SCSI functions stacks
interrupts). SCSI interrupt conditions are individually masked through the
SCSI Interrupt Enable Zero (SIEN0) register.
When performing consecutive 8-bit reads of the DMA Status (DSTAT) ,
SCSI Interrupt Status Zero (SIST0) , and SCSI Interrupt Status One
(SIST1) registers (in any order), insert a delay equivalent to 12 CLK
periods between the reads to ensure the interrupts clear properly. Also,
if reading the registers when both the ISTAT SIP and DIP bits may not
be set, read the
SCSI Interrupt Status Zero (SIST0) and SCSI Interrupt
7 6 5 4 3 2 1 0
M/A CMP SEL RSL SGE UDC RST PAR
0 0 0 0 0 0 0 0