Avago Technologies LSI53C876E User Manual
Page 45
SCSI Functional Description
2-23
If the DMA FIFO size is set to 536 bytes (bit 5 of the
register is set), subtract the 10 least significant
bits of the
register from the 10-bit
value of the DMA FIFO Byte Offset Counter, which consists of
bits [1:0] in the
register and bits [7:0]
of the
register. AND the result with 0x3FF
for a byte count between 0 and 536.
Step 2.
Read bit 7 in the
and
register to determine if any bytes are left in the
register. If bit 7 is set in the
SSTAT0 or SSTAT2, then the least significant byte or the most
significant byte is full, respectively.
Step 3.
If any wide transfers have been performed using the Chained
Move instruction, read the Wide SCSI Receive bit (
, bit 0) to determine whether a byte is left
in the
register.
Synchronous SCSI Receive –
Step 1.
If the DMA FIFO size is set to 88 bytes, subtract the seven least
significant bits of the
register from
the 7-bit value of the
register. AND the
result with ox7F for a byte count between 0 and 88.
If the DMA FIFO size is set to 536 bytes (bit 5 of the
register is set), subtract the 10 least significant
bits of the
register from the 10-bit
value of the DMA FIFO Byte Offset Counter, which consists of
bits [1:0] in the
register and bits [7:0]
of the
register. AND the result with 0x3FF
for a byte count between 0 and 536.
Step 2.
Read the
register and examine bits
[7:4], the binary representation of the number of valid bytes in
the SCSI FIFO, to determine if any bytes are left in the SCSI
FIFO.
Step 3.
If any wide transfers have been performed using the Chained
Move instruction, read the Wide SCSI Receive bit (
, bit 0) to determine whether a byte is left
in the
register.