Avago Technologies LSI53C876E User Manual
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Registers
ERL
Enable Read Line
3
This bit enables a PCI Read Line command. If this bit is
set and the chip is about to execute a read cycle other
than an opcode fetch, then the command is 0b1110.
ERMP
Enable Read Multiple
2
If this bit is set and cache mode is enabled, a Read
Multiple command is used on all read cycles when it is
legal.
BOF
Burst Opcode Fetch Enable
1
Setting this bit causes the LSI53C876 SCSI function to
fetch instructions in burst mode. Specifically, the chip
bursts in the first two Dwords of all instructions using a
single bus ownership. If the instruction is a Memory-to-
Memory Move type, the third Dword is accessed in a
subsequent bus ownership. If the instruction is an indirect
type, the additional Dword is accessed in a subsequent
bus ownership. If the instruction is a table indirect block
move type, the chip accesses the remaining two Dwords
in a subsequent bus ownership, thereby fetching the four
Dwords required in two bursts of two Dwords each. If
prefetch is enabled, this bit has no effect. This bit also
has no effect on fetches out of SCRIPTS RAM.
MAN
Manual Start Mode
0
Setting this bit prevents the LSI53C876 SCSI function
from automatically fetching and executing SCSI
SCRIPTS when the
register is written. When this bit is set, the Start DMA bit
in the
register must be set to
begin SCRIPTS execution. Clearing this bit causes the
LSI53C876 SCSI function to automatically begin fetching
and executing SCSI SCRIPTS when the
register is written. This bit normally is not
used for SCSI SCRIPTS operations.