Avago Technologies LSI53C876E - Manual (Page 149)

SCSI Registers 4-55
CIO Configured as I/O 5
This bit is defined as the Configuration I/O Enable Status
bit. This read only bit indicates if the chip is currently
enabled as I/O space.
Note: Both bits 4 and 5 may be set if the chip is dual-mapped.
CM Configured as Memory 4
This bit is defined as the configuration memory enable
status bit. This read only bit indicates if the chip is
currently enabled as memory space.
Note: Both bits 4 and 5 may be set if the chip is dual-mapped.
SRTCH SCRATCHA/B Operation 3
This bit controls the operation of the Scratch Register A
(SCRATCHA) and Scratch Register B (SCRATCHB)
registers. When it is set, SCRATCHB contains the RAM
base address value from the PCI configuration RAM
Base Address register. This is the base address for the
4 Kbytes internal RAM. In addition, the SCRATCHA
register displays the memory-mapped based address of
the chip operating registers. When this bit is cleared, the
Scratch Register A (SCRATCHA) and Scratch Register B
(SCRATCHB) registers return to normal operation.
Bit 3 is the only writable bit in this register. All other bits
are read only. When modifying this register, all other bits
must be written to zero. Do not execute a read-modify-
write to this register.
TEOP SCSI True End of Process 2
This bit indicates the status of the LSI53C876 SCSI
function’s internal TEOP signal. The TEOP signal
acknowledges the completion of a transfer through the
SCSI portion of the LSI53C876 SCSI function. When this
bit is set, TEOP is active. When this bit is clear, TEOP is
inactive.
DREQ Data Request Status 1
This bit indicates the status of the LSI53C876 SCSI
function’s internal Data Request signal (DREQ). When
this bit is set, DREQ is active. When this bit is clear,
DREQ is inactive.