3 internal arbiter, Internal arbiter – Avago Technologies LSI53C876E User Manual
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Functional Description
After each data transfer, the chip re-evaluates the burst size based on
the amount of remaining data to transfer and again selects the highest
possible multiple of the cache line size, no larger than the
burst size. The most likely scenario of this scheme is that the
chip selects the
burst size after alignment, and
issues bursts of this size. The burst size is, in effect, throttled down
toward the end of a long Memory Move or Block Move transfer until only
the cache line size burst size is left. The chip finishes the transfer with
this burst size.
Latency – In accordance with the PCI specification, the chip's latency
timer is ignored when issuing a Write and Invalidate command such that
when a latency time-out occurs, the LSI53C876 continues to transfer up
to a cache line boundary. At that point, the chip relinquishes the bus, and
finishes the transfer at a later time using another bus ownership. If the
chip is transferring multiple cache lines it continues to transfer until the
next cache boundary is reached.
PCI Target Retry – During a Write and Invalidate transfer, if the target
device issues a retry (STOP with no TRDY, indicating that no data was
transferred), the chip relinquishes the bus and immediately tries to finish
the transfer on another bus ownership. The chip issues another Write
and Invalidate command on the next ownership, in accordance with the
PCI specification.
PCI Target Disconnect – During a Write and Invalidate transfer, if the
target device issues a disconnect the LSI53C876 relinquishes the bus
and immediately tries to finish the transfer on another bus ownership.
The chip does not issue another Write and Invalidate command on the
next ownership unless the address is aligned.
2.1.3 Internal Arbiter
The PCI to SCSI controller uses a single REQ/ - GNT/ signal pair to
arbitrate for access to the PCI bus. The LSI53C876 uses a round robin
arbitration scheme to allow both SCSI functions to arbitrate for PCI bus
access.
An internal arbiter circuit allows the different bus mastering functions
resident in the chip to arbitrate among themselves for the privilege of
arbitrating for PCI bus access. There are two independent bus mastering
functions inside the LSI53C876, one for each of the SCSI functions.