Avago Technologies LSI53C876E - Manual (Page 249)

AC Characteristics 6-17
Figure 6.9 Configuration Register Read
Table 6.25 Configuration Register Read
Symbol Parameter
1
1. See note on page 6-16 regarding 3.3 V PCI Timing Changes.
Min Max Unit
t
1
Shared signal input setup time 7 – ns
t
2
Shared signal input hold time 0 – ns
t
3
CLK to shared signal output valid – 11 ns
t
1
Add In
CLK
(Driven by System)
FRAME/
(Driven by System)
AD/
(Driven by Master-Addr;
LSI53C876-Data)
C_BE/
(Driven by Master)
PAR
(Driven by Master-Addr;
LSI53C876-Data)
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C876)
STOP/
(Driven by LSI53C876)
(Driven by LSI53C876)
IDSEL
(Driven by Master)
DEVSEL/
Data Out
t
2
t
1
CMD
t
2
t
1
t
2
Byte Enable
t
2
t
1
t
3
Out In
t
2
t
2
t
1
t
3
t
3
t
3
t
1
t
2
t
3