4 pci cache mode, 1 selection of cache line size, 2 alignment – Avago Technologies LSI53C876E User Manual
Page 33: Pci cache mode
PCI Functional Description
2-11
2.1.4 PCI Cache Mode
The LSI53C876 supports the PCI specification for an 8-bit
register located in the PCI configuration space. The
register provides the ability to sense and react to nonaligned
addresses corresponding to cache line boundaries. In conjunction with
the
register, the PCI commands Read Line, Read
Multiple, and Write and Invalidate are each software enabled or disabled
to allow the user full flexibility in using these commands.
2.1.4.1 Selection of Cache Line Size
The cache logic for each bus mastering function selects a cache line size
based on the values for the burst size in the
register, and the PCI
register, whichever is appropriate.
Note:
Each bus mastering function does not automatically use the
value in its PCI
register as the cache line
size value. The chip scales the value of the
register down to the nearest binary burst size allowed
by the chip (2, 4, 8, 16, 32, 64, or 128). The SCSI function
compares this value to the DMODE burst size, then selects
the smaller as the value for the cache line size.
2.1.4.2 Alignment
The LSI53C876 uses the calculated line size value to monitor the current
address for alignment to the cache line size. When it is not aligned, the
chip attempts to align to the cache boundary by using a “smart aligning”
scheme. This means that it attempts to use the largest burst size
possible that is less than the cache line size, to reach the cache
boundary quickly with no overflow. This process is a stepping mechanism
that steps up to the highest possible burst size based on the current
address.
The stepping process begins at a 4 Dword boundary. The LSI53C876
first tries to align to a 4 Dword boundary (0x0000, 0x0010, 0x0020, etc.)
by using single Dword transfers (no bursting). Once this boundary is
reached the chip evaluates the current alignment to various burst sizes
allowed, and selects the largest possible as the next burst size, while not
exceeding the cache line size. The chip then issues this burst and
re-evaluates the alignment to various burst sizes, again selecting the