Avago Technologies LSI53C876E - Manual (Page 122)

4-28 Registers
value written to the I/O bit in SCSI Output Control Latch
(SOCL) . This bit is self-clearing. Do not set it for low level
operation.
Note: Writing to this register while not connected may cause the
loss of a selection/reselection by resetting the Connected
bit.
Register: 0x02
SCSI Control Two (SCNTL2)
Read/Write
SDU SCSI Disconnect Unexpected 7
This bit is valid in the initiator mode only. When this bit is
set, the SCSI core is not expecting the SCSI bus to enter
the Bus Free phase. If it does, an unexpected disconnect
error is generated (see the Unexpected Disconnect bit in
the
SCSI Interrupt Status Zero (SIST0) register, bit 2).
During normal SCRIPTS mode operation, this bit is set
automatically whenever the SCSI core is reselected, or
successfully selects another SCSI device. The SDU bit
should be cleared with a register write (move 0x00 to
SCSI Control Two (SCNTL2) ) before the SCSI core
expects a disconnect to occur, normally prior to sending
an Abort, Abort Tag, Bus Device Reset, Clear Queue or
Release Recovery message, or before deasserting
SACK/ after receiving a Disconnect command or
Command Complete message.
CHM Chained Mode 6
This bit determines whether or not the SCSI core is
programmed for chained SCSI mode. This bit is
automatically set by the Chained Block Move (CHMOV)
SCRIPTS instruction and is automatically cleared by the
Block Move SCRIPTS instruction (MOVE).
Chained mode primarily transfers consecutive wide data
blocks. Using chained mode facilitates partial receive
transfers and allows correct partial send behavior. When
this bit is set and a data transfer ends on an odd byte
7 6 5 4 3 2 1 0
SDU CHM SLPMD SLPHBEN WSS VUE0 VUE1 WSR
0 0 0 0 0 0 x 0