Avago Technologies LSI53C876E User Manual
Page 187
SCSI Registers
4-93
HSC
Halt SCSI Clock
5
Asserting this bit causes the internal divided SCSI clock
to come to a stop in a glitchless manner. This bit is used
for test purposes or to lower I
DD
during a power-down
mode.
DSI
Disable Single Initiator Response
4
If this bit is set, the LSI53C876 SCSI function ignores all
bus-initiated selection attempts that employ the single
initiator option from SCSI-1. In order to select the
LSI53C876 SCSI function while this bit is set, the
LSI53C876 SCSI function’s SCSI ID and the initiator’s
SCSI ID must both be asserted. Assert this bit in
SCSI-2 systems so that a single bit error on the SCSI bus
is not interpreted as a single initiator response.
CHECKHI
Check High Parity
3
If this bit is set, all devices in the SCSI system
implementation are assumed to be 16-bit. This causes
the LSI53C876 to always check the parity bit for SCSI
IDs [15:8] during bus-initiated selection or reselection,
assuming parity checking has been enabled. If an 8-bit
SCSI device attempts to select the LSI53C876 while this
bit is set, the chip ignores the selection attempt. This is
because the parity bit for IDs [15:8] is undriven. See the
description of the Enable Parity Checking bit in the
register for more information.
TTM
Timer Test Mode
2
Asserting this bit facilitates testing of the selection
time-out, general purpose, and handshake-to-handshake
timers by greatly reducing all three time-out periods.
Setting this bit starts all three timers and if the respective
bits in the
SCSI Interrupt Enable One (SIEN1)
register
are asserted, the LSI53C876 SCSI function generates
interrupts at time-out. This bit is intended for internal
manufacturing diagnosis and should not be used.
CSF
Clear SCSI FIFO
1
Setting this bit causes the “full flags” for the SCSI FIFO
to be cleared. This empties the FIFO. This bit is
self-clearing. In addition to the SCSI FIFO pointers, the
, and SODR full bits in the
and
are cleared.