Chip test four (ctest4), Register: 0x21 – Avago Technologies LSI53C876E User Manual
Page 153
SCSI Registers
4-59
Register: 0x21
Chip Test Four (CTEST4)
Read/Write
BDIS
Burst Disable
7
When set, this bit causes the LSI53C876 SCSI function
to perform back-to-back cycles for all transfers. When this
bit is cleared, back-to-back transfers for opcode fetches
and burst transfers for data moves are performed.
ZMOD
High Impedance Mode
6
Setting this bit causes the LSI53C876 SCSI function to
place all output and bidirectional pins into a high
impedance state. In order to read data out of the
LSI53C876 SCSI function, clear this bit. This bit is
intended for board-level testing only. Do not set this bit
during normal system operation. To use this feature set
the bit in both SCSI Function A and SCSI Function B.
ZSD
SCSI Data High Impedance
5
Setting this bit causes the LSI53C876 SCSI function to
place the SCSI data bus SD[15:0] and the parity lines
SDP[1:0] in a high impedance state. In order to transfer
data on the SCSI bus, clear this bit.
SRTM
Shadow Register Test Mode
4
Setting this bit allows access to the shadow registers
used by Memory-to-Memory Move operations. When this
bit is set, register accesses to the
and
registers are directed to
the shadow copies STEMP (Shadow TEMP) and SDSA
(Shadow DSA). The registers are shadowed to prevent
them from being overwritten during a Memory-to-Memory
Move operation. The
and
registers contain the base address
used for table indirect calculations, and the address
pointer for a call or return instruction, respectively. This bit
is intended for manufacturing diagnostics only and should
not be set during normal operations.
7
6
5
4
3
2
0
BDIS
ZMOD
ZSD
SRTM
MPEE
FBL[2:0]
0
0
0
0
0
0
0
0