Avago Technologies LSI53C876E - Manual (Page 92)

3-20 Signal Descriptions
3.5 Power and Ground Signals
Table 3.16 describes the signals for the Power and Ground Signals
group.
TDI 61, W5 I N/A Test Data In. Serial test instructions are received
by the JTAG test logic at this pin. It has a static
pull-up.
TDO 63, V6 O N/A Test Data Out. This pin is the serial output for test
instructions and data from the JTAG test logic.
Table 3.15 Test Interface Signals (Cont.)
Table 3.16 Power and Ground Signals
Name Pin No. Type Strength Description
V
DD
-IO 6, 13, 22, 31, 39, 47, 55, 206,
B3, E3, G2, K2, M3, P3, U2, W4 P N/A Power for PCI bus drivers/receivers.
V
SS
2, 9, 15, 19, 24, 29, 35, 41, 45,
51, 57, 204,
A1, C2, D4, D5, D8, D13, D17,
F3, H3, H4, H17, J3, K1, M1,
N3, N4, N17, T1, U1, U4, U5,
U8, U13, U17, W2 G N/A Ground for PCI bus drivers/receivers.
V
DD
-S 90, 124, 138, 172,
A10, B9,C14, F20, K20, N18,
U14, V9, Y13 P N/A Power for SCSI bus drivers/receivers.
V
SS
-S 94, 99, 105, 110, 115, 120, 142,
147, 153, 158, 163, 168 G N/A Ground for SCSI bus drivers/receivers.
V
DD
-C 64, 131, 201,
C5, J17, U7 P N/A Power for core logic.
V
SS
-C 67, 129, 198,
C6, J19, V7 G N/A Ground for core logic.
V
DD
75, 186 P N/A Power for other I/O.
V
SS
72, 85, 133, 178, 188 G N/A Ground for other I/O.