Avago Technologies LSI53C876E - Manual (Page 167)

SCSI Registers 4-73
Register: 0x40
SCSI Interrupt Enable Zero (SIEN0)
Read/Write
This register contains the interrupt mask bits corresponding to the
interrupting conditions described in the
SCSI Interrupt Status Zero
(SIST0) register. An interrupt is masked by clearing the appropriate mask
bit. For more information on interrupts, see Chapter 2, “Functional
Description.”
M/A SCSI Phase Mismatch - Initiator Mode;
SCSI ATN Condition - Target Mode
7
Setting this bit allows the LSI53C876 to generate an
interrupt when a Phase Mismatch or ATN condition
occurs. In initiator mode, this bit is set when the SCSI
phase asserted by the target and sampled during SREQ/
does not match the expected phase in the
SCSI Output
Control Latch (SOCL) register. This expected phase is
automatically written by SCSI SCRIPTS. In target mode,
this bit is set when the initiator asserts SATN/. See the
Disable Halt on Parity Error or SATN/ Condition bit in the
SCSI Control One (SCNTL1) register for more
information on when this status is actually raised.
CMP Function Complete 6
Setting this bit allows the LSI53C876 to generate an
interrupt when a full arbitration and selection sequence
has completed.
SEL Selected 5
Setting this bit allows the LSI53C876 to generate an
interrupt when the LSI53C876 has been selected by
another SCSI device. Set the Enable Response to
Selection bit in the
SCSI Chip ID (SCID) register for this
to occur.
7 6 5 4 3 2 1 0
M/A CMP SEL RSL SGE UDC RST PAR
0 0 0 0 0 0 0 0