Avago Technologies LSI53C876E - Manual (Page 137)

SCSI Registers 4-43
ABRT Aborted 4
This bit is set when an abort condition occurs. An abort
condition occurs when a software abort command is
issued by setting bit 7 of the
Interrupt Status (ISTAT)
register.
SSI Single Step Interrupt 3
If the Single Step Mode bit in the DMA Control (DCNTL)
register is set, this bit is set and an interrupt is generated
after successful execution of each SCRIPTS instruction.
SIR SCRIPTS Interrupt Instruction Received 2
This status bit is set whenever an Interrupt instruction is
evaluated as true.
R Reserved 1
IID Illegal Instruction Detected 0
This status bit is set any time an illegal or reserved
instruction opcode is detected, whether the LSI53C876
SCSI function is operating in single step mode or
automatically executing SCSI SCRIPTS.
Any of the following conditions during instruction
execution also set this bit:
•
The LSI53C876 SCSI function is executing a Wait
Disconnect instruction and the SCSI REQ line is
asserted without a disconnect occurring.
•
A Block Move instruction is executed with 0x000000
loaded into the
DMA Byte Counter (DBC) register,
indicating there are zero bytes to move.
•
During a Transfer Control instruction, the Compare
Data (bit 18) and Compare Phase (bit 17) bits are set
in the
DMA Byte Counter (DBC) register while the
LSI53C876 SCSI function is in target mode.
•
During a Transfer Control instruction, the Carry Test
bit (bit 21) is set and either the Compare Data (bit 18)
or Compare Phase (bit 17) bit is set.
•
A Transfer Control instruction is executed with the
reserved bit 22 set.
•
A Transfer Control instruction is executed with the
Wait for Valid phase bit (bit 16) set while the chip is in
target mode.