Avago Technologies LSI53C876E - Manual (Page 53)

SCSI Functional Description 2-31
2.2.8.5 Wide Ultra SCSI Synchronous Transfers
Wide Ultra SCSI is an extension of current Fast SCSI synchronous
transfer specifications. It allows synchronous transfer periods to be
negotiated down as low as 50 ns, which is half the 100 ns period allowed
under Fast SCSI. This allows a maximum transfer rate of 40 Mbytes/s on
a 16-bit SCSI bus. The LSI53C876 requires that the 40 MHz clock is
doubled by the internal clock doubler (see the
SCSI Test One (STEST1)
register description) to perform Wide Ultra SCSI transfers. In addition,
the following bit values affect the chip’s ability to support Wide Ultra SCSI
synchronous transfer rates:
•
Clock Conversion Factor bits, SCSI Control Three (SCNTL3) register
bits [2:0] and Synchronous Clock Conversion Factor bits, SCNTL3
register bits [6:4]. These fields now support a value of 101 (binary),
allowing the SCLK frequency to be divided down by 4. This allows
systems with a 40 MHz clock to operate at Fast SCSI-2 transfer rates
as well as Wide Ultra SCSI rates, if needed.
•
Wide Ultra SCSI Mode Enable bit, SCSI Control Three (SCNTL3)
register, bit 7. Setting this bit enables Wide Ultra SCSI synchronous
transfers in systems that have a 40 MHz clock using the internal
clock doubler.
•
TolerANT Enable bit, SCSI Test Three (STEST3) register, bit 7.
Setting this bit enables active negation.