Avago Technologies LSI53C876E User Manual
Page 128
4-34
Registers
TP[2:0]
SCSI Synchronous Transfer Period
[7:5]
These bits determine the SCSI synchronous transfer
period used by the LSI53C876 SCSI function when
sending synchronous SCSI data in either the initiator or
target mode. These bits control the programmable
dividers in the chip.
For Wide Ultra SCSI transfers, the ideal transfer period
is 4, and 5 is acceptable. Setting the transfer period to a
value greater than 5 is not recommended.
The synchronous transfer period the LSI53C876 should
use when transferring SCSI data is determined in the
following example.
The LSI53C876 is connected to a hard disk which can
transfer data at 10 Mbytes/s synchronously. The
LSI53C876 SCSI function’s SCLK is running at 40 MHz.
The synchronous transfer period (SXFERP) is found as
follows:
SXFERP = Period/SSCP + ExtCC
Period = 1
÷
Frequency = 1
÷
10 Mbytes/s = 100 ns
SSCP = 1
÷
SSCF = 1
÷
40 MHz = 25 ns
(This SCSI synchronous core clock is determined in
, bits [6:4], ExtCC = 1 if
, bit 7 is asserted and the
LSI53C876 is sending data. ExtCC = 0 if the LSI53C876
is receiving data.)
SXFERP = 100
÷
25 = 4
TP2
TP1
TP0
XFERP
0
0
0
4
0
0
1
5
0
1
0
6
0
1
1
7
1
0
0
8
1
0
1
9
1
1
0
10
1
1
1
11