Avago Technologies LSI53C876E - Manual (Page 39)

SCSI Functional Description 2-17
1. Use the RST/ pin as a boundary scan compliance pin. When the pin
deasserts, the device is boundary scan compliant and when it
asserts, the device is noncompliant. To maintain compliance the
RST/ pin must be driven high.
2. When RST/ asserts during boundary scan testing the expected
output on the SCSI pins must be the HIGH-Z condition, and not what
is contained in the boundary scan data registers for the SCSI pin
output cells.
2.2.4 SCSI Loopback Mode
The LSI53C876 loopback mode allows testing of both initiator and target
functions and, in effect, lets the chip communicate with itself. When the
Loopback Enable bit is set in the
SCSI Test Two (STEST2) register, bit 4,
the LSI53C876 allows control of all SCSI signals, whether the chip is
operating in the initiator or target mode. For more information on this
mode of operation, refer to the
SCSI SCRIPTS Processors Programming
Guide .
2.2.5 Parity Options
The LSI53C876 implements a flexible parity scheme that allows control
of the parity sense, allows parity checking to be turned on or off, and has
the ability to deliberately send a byte with bad parity over the SCSI bus
to test parity error recovery procedures.
Table 2.2 defines the bits that
are involved in parity control and observation. Table 2.3 describes the
parity control function of the Enable Parity Checking and Assert SCSI
Even Parity bits in the
SCSI Control One (SCNTL1) register, bit 2.
Table 2.4 describes the options available when a parity error occurs.
Figure 2.2 shows where parity checking is done in the LSI53C876.