Avago Technologies LSI53C876E - Manual (Page 312)

IX-8 Index
SCSI serial EEPROM access 2-45
SCSI status one register 4-46
SCSI status two register 4-48
SCSI status zero register 4-44
SCSI synchronous offset maximum 4-88
SCSI synchronous offset zero bit 4-87
SCSI test one register 4-88
SCSI test three register 4-92
SCSI test two register 4-90
SCSI test zero register 4-87
SCSI timer one register 4-85
SCSI timer zero register 4-83
SCSI transfer register 4-33
SCSI true end of process bit 4-55
SCSI valid bit 4-40
SCSI wide residue register 4-81
SCTRL/ 3-14
,
3-15
,
3-16
,
3-17
SD/[15:0] 3-14
,
3-15
,
3-16
,
3-17
SDID register 4-36
SDIR 3-16
SDIR[15:0] 3-17
SDMS 1-3
SDP/[1:0] 3-14
,
3-15
SEL 2-35
select with SATN/ on a start sequence bit 4-23
selected bit 4-73
,
4-77
selection of cache line size 2-11
selection or reselection time-out bit 4-75
,
4-79
selection response logic test bits 4-87
semaphore bit 4-51
serial EEPROM interface 2-45
mode A operation 2-45
mode B operation 2-46
mode C operation 2-46
mode D operation 2-48
register 0x2C 4-11
register 0x2E 4-12
SERR/ 3-9
SFBR register 4-38
shadow register test mode bit 4-59
SI_O/ 3-14
,
3-15
SI_O/ status bit 4-41
SIDL least significant byte full bit 4-44
SIDL most significant byte full bit 4-48
SIDL register 4-94
SIEN0 2-35
SIEN0 register 4-73
SIEN1 2-35
SIEN1 register 4-75
SIGP bit 4-51
,
4-54
single-ended operation 2-24
single-step interrupt bit 4-43
,
4-69
single-step mode bit 4-71
SIP 2-34
,
2-37
,
2-38
SIST0 2-34
,
2-37
,
2-39
SIST0 register 4-76
SIST1 2-34
,
2-37
,
2-39
SIST1 register 4-79
slow ROM pin 3-22
SLPAR high byte enable 4-29
SLPAR mode bit 4-29
SLPAR register 4-80
SMSG/ 3-14
,
3-15
SMSG/ status bit 4-41
SOCL least significant byte full bit 4-45
SOCL register 4-39
SODL most significant byte full bit 4-48
SODL register 4-95
SODR least significant byte full bit 4-44
SODR most significant byte full bit 4-48
software reset bit 4-51
source I/O-memory enable bit 4-67
special cycle command 2-5
SREQ 2-38
SREQ/ 3-14
,
3-15
SREQ/ status bit 4-41
SRST/ 3-14
,
3-15
SSEL/ 3-14
,
3-15
SSEL/ status bit 4-41
SSID register 4-40
SSTAT0 register 4-44
SSTAT1 register 4-46
SSTAT2 register 4-48
stacked interrupts 2-37
start DMA operation bit 4-71
start SCSI transfer 4-27
start sequence bit 4-23
STEST0 register 4-87
STEST1 register 4-88
STEST2 register 4-90
STEST3 register 4-92
STIME0 register 4-83
STIME1 register 4-85
stop 3-8
subsystem ID 2-46
,
2-47
(SID[15:0]) 4-12
subsystem vendor ID 2-46
,
2-47
(SVID[15:0]) 4-11
SWIDE register 4-81
SXFER register 4-33
synchronous clock conversion factor bits 4-31
synchronous data transfer rates 2-30
synchronous operation 2-30
synchronous SCSI receive 2-23
synchronous SCSI send 2-22
synchronous transfer period bits 4-34
system signals 3-6
T
target mode bit 4-24
target ready 3-8
TCK 3-19
TDI 3-20
TDO 3-20
TEMP register 4-57
temporary register 4-57
termination 2-28
terminator networks 2-28
testability 1-6
TESTIN/ 3-19
TGS 3-16
,
3-17
timer test mode bit 4-93
timing diagrams 6-15
TMS 3-19
TolerANT enable bit 2-33
,
4-92
TolerANT SCSI 1-4
TolerANT technology 1-7
benefits 1-4
extend SREQ/SACK filtering bit 4-91
TolerANT enable bit 4-92
totem pole output 3-5