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Avago Technologies LSI53C876E User Manual

Page 123

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SCSI Registers

4-29

boundary, the LSI53C876 SCSI function stores the last
byte in the

SCSI Wide Residue (SWIDE)

register during

a receive operation, or in the

SCSI Output Data Latch

(SODL)

register during a send operation. This byte is

combined with the first byte from the subsequent transfer
so that a wide transfer is completed.

For more information, see

Section 2.2.11, “Chained Block

Moves,”

in

Chapter 2, “Functional Description.”

SLPMD

SLPAR Mode Bit

5

If this bit is cleared, the

SCSI Longitudinal Parity (SLPAR)

register functions as a byte-wide longitudinal parity
register. If this bit is set, the SLPAR functions as a
word-wide longitudinal parity function. The high or low
byte of the SLPAR word is accessible through the

SCSI

Longitudinal Parity (SLPAR)

register. Which byte is

accessible is controlled by the SLPHEN bit.

SLPHBEN

SLPAR High Byte Enable

4

If this bit is cleared, the low byte of the SLPAR word is
present in the SLPAR register. If this bit is set, the high
byte of the SLPAR word is present in the

SCSI Longitu-

dinal Parity (SLPAR)

register.

WSS

Wide SCSI Send

3

When read, this bit returns the value of the Wide SCSI
Send (WSS) flag. Asserting this bit clears the WSS flag.
This clearing function is self-clearing.

When the WSS flag is high following a wide SCSI send
operation, the SCSI core is holding a byte of “chain” data
in the

SCSI Output Data Latch (SODL)

register. This data

becomes the first low-order byte sent when married with
a high-order byte during a subsequent data send transfer.

Performing a SCSI receive operation clears this bit. Also,
performing any nonwide transfer clears this bit.

VUE0

Vendor Unique Enhancement, Bit 0

2

This bit is a read only value indicating whether the group
code field in the SCSI instruction is standard or vendor
unique. If cleared, the bit indicates standard group codes;
if set, the bit indicates vendor unique group codes. The
value in this bit is reloaded at the beginning of all
asynchronous target receives.