Avago Technologies LSI53C876E - Manual (Page 55)

SCSI Functional Description 2-33
SCSI timing information. In addition to the guidelines in the draft
standard, make the following software and hardware adjustments to
accommodate Wide Ultra SCSI transfers:
•
Set the Wide Ultra SCSI Enable bit to enable Wide Ultra SCSI
transfers.
•
Set the TolerANT Enable bit, bit 7 in the SCSI Test Three (STEST3)
register, whenever the Wide Ultra SCSI Enable bit is set.
•
Do not extend the SREQ/SACK filtering period with SCSI Test Two
(STEST2), bit 1.
•
Use a 40 MHz SCSI clock with an internal clock doubler.
2.2.10 Interrupt Handling
The SCRIPTS processors in the LSI53C876 performs most functions
independently of the host microprocessor. However, certain interrupt
situations must be handled by the external microprocessor. This section
explains all aspects of interrupts as they apply to the LSI53C876.
2.2.10.1 Polling and Hardware Interrupts
The external microprocessor is informed of an interrupt condition by
polling or hardware interrupts. Polling means that the microprocessor
must continually loop and read a register until it detects a bit set that
indicates an interrupt. This method is the fastest, but it wastes CPU time
that could be used for other system tasks. The preferred method of
detecting interrupts in most systems is hardware interrupts. In this case,
the LSI53C876 asserts the Interrupt Request (INTA/ or INTB/) line that
interrupts the microprocessor, causing the microprocessor to execute an
interrupt service routine. A hybrid approach would use hardware
interrupts for long waits, and use polling for short waits.
2.2.10.2 Registers
The registers in the LSI53C876 that are used for detecting or defining
interrupts are the
Interrupt Status (ISTAT) , SCSI Interrupt Status Zero
(SIST0) , SCSI Interrupt Status One (SIST1) , DMA Status (DSTAT) , SCSI
Interrupt Enable Zero (SIEN0) , SCSI Interrupt Enable One (SIEN1) , DMA
Control (DCNTL) , and DMA Interrupt Enable (DIEN) .