Index ix-5 – Avago Technologies LSI53C876E User Manual
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Index
IX-5
operating registers (Cont.)
SCSI wide residue
temporary stack
P
PAR
parallel ROM interface
parity
parity error
parity error bit
PCI addressing
PCI and external memory interface timings
symbols and parameters
PCI bus commands and functions supported
PCI cache line size register
PCI cache mode
cache line size enable bit
enable read multiple bit
write and invalidate enable bit
PCI commands
PCI configuration registers
PCI functional description
PCI I/O space
PCI interface pins
PCI interface signals
PCI interrupt signals
PCI memory space
PCI performance
PCI target disconnect
PCI target retry
PERR/
phase mismatch bit
physical dword address and data
polling
power management
isolated power supplies
power state D0
power state D1
power state D2
power state D3
register 0x40, capability ID
register 0x41, next item pointer
register 0x42, power management capabilities
register 0x44, control/status
register 0x46, PMCSR BSE
register 0x47, data
prefetch enable bit
prefetch flush bit
R
RAM, see also SCRIPTS RAM
read line mode
read multiple with read line enabled
read/write instructions
register addresses
operating registers
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10–0x13
0x14
0x18
0x19
0x1A
0x1B
0x1C–0x1F
0x20
0x21
0x22
0x23
0x24–0x26
0x27
0x28–0x2B
0x2C–0x2F
0x30–0x33
0x34–0x37
0x38
0x39
0x3A
0x3B
0x3C–0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50–0x51
0x54–0x55
0x58–0x59
0x5C–0x5F
0x60–0x70
register bits
abort operation
aborted
,
always wide SCSI
arbitration in progress
arbitration mode
arbitration priority encoder test
assert even SCSI parity (force bad parity))
assert SATN/ on parity error
assert SCSI ACK/ signal
assert SCSI ATN/ signal
assert SCSI BSY/ signal
assert SCSI C_D/ signal
assert SCSI data bus
assert SCSI I_O/ signal
assert SCSI MSG/ signal