Avago Technologies LSI53C876E - Manual (Page 78)

3-6 Signal Descriptions
3.1 PCI Interface Signals
The PCI interface signals are organized into the following functional
groups:
System Signals , Address and Data Signals , Interface Control
Signals , Arbitration Signals , Error Reporting Signals , PCI Interrupt
Signals , and GPIO Interface Signals .
3.1.1 System Signals
Table 3.1 describes the signals for the System Signals group.
Table 3.1 System Signals
Name Pin No. Type Strength Description
CLK 197, D7 I N/A Clock provides timing for all transactions on the PCI bus and is
an input to every PCI device. All other PCI signals are sampled
on the rising edge of CLK, and other timing parameters are
defined with respect to this edge. Clock can optionally serve as
the SCSI core clock, but this may effect fast SCSI transfer rates.
RST/ 196, A5 I N/A Reset forces the PCI sequencer of each device to a known state.
All T/S and S/T/S signals are forced to a high impedance state,
and all internal logic is reset. The RST/ input is synchronized
internally to the rising edge of CLK. The CLK input must be
active while RST/ is active to properly reset the device.