Avago Technologies LSI53C876E User Manual
Page 139
SCSI Registers
4-45
sending data synchronously. It is not readable or writable
by the user. It is possible to use this bit to determine how
many bytes reside in the chip when an error occurs.
OLF
SODL Least Significant Byte Full
5
This bit is set when the least significant byte in the
contains data. The SODL
register is the interface between the DMA logic and the
SCSI bus. In synchronous mode, data is transferred from
the host bus to the SODL register, and then to the SCSI
Output Data Register (SODR, a hidden buffer register
which is not accessible) before being sent to the SCSI
bus. In asynchronous mode, data is transferred from the
host bus to the
register,
and then to the SCSI bus. The SODR buffer register is
not used for asynchronous transfers. It is possible to use
this bit to determine how many bytes reside in the chip
when an error occurs.
AIP
Arbitration in Progress
4
Arbitration in Progress (AIP = 1) indicates that the
LSI53C876 SCSI function has detected a Bus Free
condition, asserted BSY, and asserted its SCSI ID onto
the SCSI bus.
LOA
Lost Arbitration
3
When set, LOA indicates that the LSI53C876 SCSI
function has detected a bus free condition, arbitrated for
the SCSI bus, and lost arbitration due to another SCSI
device asserting the SEL/ signal.
WOA
Won Arbitration
2
When set, WOA indicates that the LSI53C876 SCSI
function has detected a Bus Free condition, arbitrated for
the SCSI bus and won arbitration. The arbitration mode
selected in the
register
must be full arbitration and selection to set this bit.
RST/
SCSI RST/ Signal
1
This bit reports the current status of the SCSI RST/
signal, and the RST signal (bit 3) in the
register. This bit is not latched and may
change as it is read.