Avago Technologies LSI53C876E - Manual (Page 171)

SCSI Registers 4-77
Status One (SIST1) registers before the DMA Status (DSTAT) register to
avoid missing a SCSI interrupt. For more information on interrupts, refer
to
Chapter 2, “Functional Description.”
M/A Initiator Mode: Phase Mismatch;
Target Mode: SATN/ Active
7
In the initiator mode, this bit is set if the SCSI phase
asserted by the target does not match the instruction.
The phase is sampled when SREQ/ is asserted by the
target. In target mode, this bit is set when the SATN/
signal is asserted by the initiator.
CMP Function Complete 6
This bit is set when an arbitration only or full arbitration
sequence is completed.
SEL Selected 5
This bit is set when the LSI53C876 SCSI function is
selected by another SCSI device. The Enable Response
to Selection bit must be set in the
SCSI Chip ID (SCID)
register (and the RESPID register must hold the chip’s
ID) for the LSI53C876 SCSI function to respond to
selection attempts.
RSL Reselected 4
This bit is set when the LSI53C876 SCSI function is
reselected by another SCSI device. The Enable
Response to Reselection bit must be set in the
SCSI
Chip ID (SCID) register (and the RESPID register must
hold the chip’s ID) for the LSI53C876 SCSI function to
respond to reselection attempts.
SGE SCSI Gross Error 3
This bit is set when the LSI53C876 SCSI function
encounters a SCSI Gross Error Condition. The following
conditions can result in a SCSI Gross Error Condition:
•
Data Underflow – reading the SCSI FIFO when
register when no data is present.
•
Data Overflow – writing too many bytes to the SCSI
FIFO, or the synchronous offset causes overwriting
the SCSI FIFO.
•
Offset Underflow – the LSI53C876 SCSI function is
operating in target mode and a SACK/ pulse is
received when the outstanding offset is zero.