Avago Technologies LSI53C876E - Manual (Page 114)

4-20 Registers
Register: 0x47
Data
Read Only
DATA Data [7:0]
This register applies only to the LSI53C876E and
provides an optional mechanism for the function to report
state-dependent operating data. The LSI53C876E
returns 0x00 as the default value.
4.2 SCSI Registers
This section contains descriptions of all LSI53C876 SCSI registers.
Table 4.2 , the register map, lists registers by operating and configuration
addresses. The terms “set” and “assert” refer to bits that are
programmed to a binary one. Similarly, the terms “deassert,” “clear,” and
“reset” refer to bits that are programmed to a binary zero. Write any bits
marked as reserved to zero; mask all information read from them.
Reserved bit functions may change at any time. Unless otherwise
indicated, all bits in registers are active HIGH, that is, the feature is
enabled by setting the bit. The bottom row of every register diagram
shows the default register values, which are enabled after the chip is
powered on or reset.
Note: The only register that the host CPU can access while the
LSI53C876 is executing SCRIPTS is the
Interrupt Status
(ISTAT) register. Attempts to access other registers
interferes with the operation of the chip. However, all
operating registers are accessible with SCRIPTS. All read
data is synchronized and stable when presented to the PCI
bus.
7 0
DATA
0 0 0 0 0 0 0 0