13 memory write and invalidate command – Avago Technologies LSI53C876E User Manual
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PCI Functional Description
2-9
2.1.2.13 Memory Write and Invalidate Command
The Memory Write and Invalidate command is identical to the Memory
Write command, except that it additionally guarantees a minimum
transfer of one complete cache line; that is to say, the master intends to
write all bytes within the addressed cache line in a single PCI transaction
unless interrupted by the target. This command requires implementation
of the PCI
register at address 0x0C in the PCI
configuration space. The LSI53C876 enables Memory Write and
Invalidate cycles when bit 0 (WRIE) in the
register and bit 4 (WIE) in the PCI
register are set. When the
following conditions are met, Memory Write and Invalidate commands
are issued:
•
The CLSE bit (Cache Line Size Enable,
register, bit 7), WRIE bit (Write and Invalid Enable,
register, bit 0), and PCI configuration Command register,
bit 4 are set.
•
The
register for each function contains a legal burst
size value (2, 4, 8, 16, 32, 64, or 128) and that value is less than or
equal to the
burst size.
•
The chip has enough bytes in the DMA FIFO to complete at least
one full cache line burst.
•
The chip is aligned to a cache line boundary.
When these conditions are met, the LSI53C876 issues a Write and
Invalidate command instead of a Memory Write command during all PCI
write cycles.
Multiple Cache Line Transfers – The Write and Invalidate command
can write multiple cache lines of data in a single bus ownership. The chip
issues a burst transfer as soon as it reaches a cache line boundary. The
size of the transfer is not automatically the cache line size, but rather a
multiple of the cache line size as specified in Revision 2.1 of the PCI
specification. The logic selects the largest multiple of the cache line size
based on the amount of data to transfer, with the maximum allowable
burst size determined from the
burst size bits, and
, bit 2. If multiple cache line size transfers are
not desired, set the
burst size to exactly the cache
line size and the chip only issues single cache line transfers.