Dma fifo, Dfifo), Dma fifo (dfifo) – Avago Technologies LSI53C876E User Manual
Page 152: Register: 0x20
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Registers
Register: 0x20
DMA FIFO (DFIFO)
Read/Write
BO
Byte Offset Counter
[7:0]
These bits, along with bits [1:0] in the
register, indicate the amount of data
transferred between the SCSI core and the DMA core. It
determines the number of bytes in the DMA FIFO when
an interrupt occurs. These bits are unstable while data is
being transferred between the two cores. Once the chip
has stopped transferring data, these bits are stable.
The DFIFO register counts the number of bytes
transferred between the DMA core and the SCSI core.
The
register counts the
number of bytes transferred across the host bus. The
difference between these two counters represents the
number of bytes remaining in the DMA FIFO.
The following steps determine how many bytes are left in
the DMA FIFO when an error occurs, regardless of the
transfer direction:
•
If the DMA FIFO size is set to 88 bytes, subtract the
seven least significant bits of the
register from the 7-bit value of the DFIFO
register. If the DMA FIFO size is set to 536 bytes
(using bit 5 of the CTEST register), subtract the
10 least significant bits of the
register from the 10-bit value of the DMA FIFO
Byte Offset Counter, which is made up of the CTEST
register (bits 1 and 0) and the
register (bits [7:0]).
•
If the DMA FIFO size is set to 88 bytes, AND the
result with 0x7F for a byte count between zero and 64.
If the DMA FIFO size is set to 536 bytes, AND the
result with 0x3FF for a byte count between zero and
536.
7
0
BO
x
0
0
0
0
0
0
0