Avago Technologies LSI53C876E - Manual (Page 229)

Load and Store Instructions 5-39
5.8.1 First Dword
IT[2:0] Instruction Type [31:29]
These bits should be 0b111, indicating the Load and
Store instruction.
DSA DSA Relative 28
When this bit is cleared, the value in the DMA SCRIPTS
Pointer Save (DSPS) is the actual 32-bit memory address
to perform the Load and Store to/from. When this bit is
set, the chip determines the memory address to perform
the Load and Store to/from by adding the 24 bit signed
offset value in the
DMA SCRIPTS Pointer Save (DSPS)
to the Data Structure Address (DSA) .
R Reserved [27:26]
NF No Flush (Store instruction only) 25
When this bit is set, the LSI53C876 performs a Store
without flushing the prefetch unit. When this bit is cleared,
the Store instruction automatically flushes the prefetch
unit. Use No Flush if the source and destination are not
within four instructions of the current Store instruction.
This bit is has no effect on the Load instruction.
Note: This bit has no effect unless the Prefetch Enable bit in the
DMA Control (DCNTL) register is set. For information on
SCRIPTS instruction prefetching, see Chapter 2, “Func-
tional Description.”
LS Load and Store 24
When this bit is set, the instruction is a Load. When
cleared, it is a Store.
R Reserved 23
RA[6:0] Register Address [22:16]
A[6:0] selects the register to Load and Store to/from
within the LSI53C876.
R Reserved [15:3]
BC Byte Count [2:0]
This value is the number of bytes to Load and Store.