Avago Technologies LSI53C876E User Manual
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Functional Description
ISTAT – The
is the only register that can be
accessed as a slave during SCRIPTS operation. Therefore, it is the
register that is polled when polled interrupts are used. It is also the first
register that should be read after the INTA/ (or INTB/) pin is asserted in
association with a hardware interrupt. The INTF (Interrupt-on-the-Fly) bit
should be the first interrupt serviced. It must be written to one to be
cleared. This interrupt must be cleared before servicing any other
interrupts.
If the SIP bit in the
register is set, then a
SCSI-type interrupt has occurred and the
and
SCSI Interrupt Status One (SIST1)
registers should be read.
If the DIP bit in the
register is set, then a
DMA-type interrupt has occurred and the
register
should be read.
SCSI-type and DMA-type interrupts may occur simultaneously, so in
some cases both SIP and DIP may be set.
SIST0 and SIST1 – The
SCSI Interrupt Status Zero (SIST0)
and
registers contain the SCSI-type interrupt
bits. Reading these registers determines which condition or conditions
caused the SCSI-type interrupt, and clears that SCSI interrupt condition.
If the LSI53C876 is receiving data from the SCSI bus and a fatal interrupt
condition occurs, the chip attempts to send the contents of the DMA
FIFO to memory before generating the interrupt.
If the LSI53C876 is sending data to the SCSI bus and a fatal SCSI
interrupt condition occurs, data could be left in the DMA FIFO. Because
of this the DMA FIFO Empty (DFE) bit in
should be
checked.
If this bit is cleared, set the CLF (Clear DMA FIFO) and CSF (Clear SCSI
FIFO) bits before continuing. The CLF bit is bit 2 in
. The CSF bit is bit 1 in
DSTAT – The
register contains the DMA-type
interrupt bits. Reading this register determines which condition or
conditions caused the DMA-type interrupt, and clears that DMA interrupt
condition. Bit 7 in
, DFE, is purely a status bit; it will
not generate an interrupt under any circumstances and is not cleared