Avago Technologies LSI53C876E User Manual
Page 165
SCSI Registers
4-71
SSM
Single Step Mode
4
Setting this bit causes the LSI53C876 SCSI function to
stop after executing each SCRIPTS instruction, and
generate a single step interrupt. When this bit is cleared
the LSI53C876 SCSI function does not stop after each
instruction. It continues fetching and executing
instructions until an interrupt condition occurs. For normal
SCSI SCRIPTS operation, keep this bit clear. To restart
the LSI53C876 SCSI function after it generates a
SCRIPTS Step interrupt, read the
and
registers to recognize
and clear the interrupt. Then set the START DMA bit in
this register.
INTM
INTA Mode
3
When set, this bit enables a totem pole driver for the
INTA/, or INTB/ pin. When cleared, this bit enables an
open drain driver for the INTA/, or INTB/, pin with an
internal weak pull-up. This bit is reset at power up. The
bit should remain clear to retain full PCI compliance.
STD
Start DMA Operation
2
The LSI53C876 SCSI function fetches a SCSI SCRIPTS
instruction from the address contained in the
register when this bit is set. This
bit is required if the LSI53C876 SCSI function is in one
of the following modes:
•
Manual start mode – Bit 0 in the
register is set
•
Single step mode – Bit 4 in the
register is set
When the LSI53C876 SCSI function is executing
SCRIPTS in manual start mode, the Start DMA bit must
be set to start instruction fetches, but need not be set
again until an interrupt occurs. When the LSI53C876
SCSI function is in single step mode, set the Start DMA
bit to restart execution of SCRIPTS after a single step
interrupt.
IRQD
INTA, INTB Disable
1
Setting this bit disables the INTA (for SCSI Function A),
or INTB (for SCSI Function B) pin. Clearing the bit
enables normal operation. As with any other register