Dma status (dstat), Status (dstat), Dma status – Avago Technologies LSI53C876E User Manual
Page 136: Dstat), Register: 0x0c
4-42
Registers
Register: 0x0C
DMA Status (DSTAT)
Read Only
Reading this register clears any bits that are set at the time the register
is read, but does not necessarily clear the register in case additional
interrupts are pending (the LSI53C876 SCSI functions stacks interrupts).
The DIP bit in the
register is also cleared. It is
possible to mask DMA interrupt conditions individually through the
register.
When performing consecutive 8-bit reads of the
,
SCSI Interrupt Status Zero (SIST0)
, and
registers (in any order), insert a delay equivalent to 12 CLK
periods between the reads to ensure that the interrupts clear properly.
See
Chapter 2, “Functional Description,”
for more information on
interrupts.
DFE
DMA FIFO Empty
7
This status bit is set when the DMA FIFO is empty. It is
possible to use it to determine if any data resides in the
FIFO when an error occurs and an interrupt is generated.
This bit is a pure status bit and does not cause an
interrupt.
MDPE
Master Data Parity Error
6
This bit is set when the LSI53C876 SCSI function as a
master detects a data parity error, or a target device
signals a parity error during a data phase. This bit is
completely disabled by the Master Parity Error Enable bit
(bit 3 of
BF
Bus Fault
5
This bit is set when a PCI bus fault condition is detected.
A PCI bus fault can only occur when the LSI53C876
SCSI function is bus master, and is defined as a cycle
that ends with a Bad Address or Target Abort Condition.
7
6
5
4
3
2
1
0
DFE
MDPE
BF
ABRT
SSI
SIR
R
IID
1
0
0
0
0
0
x
0