Avago Technologies LSI53C876E - Manual (Page 282)

6-50 Electrical Characteristics
Figure 6.25 Read Cycle, Slow Memory (
≥
128 Kbytes)
Table 6.39 Read Cycle, Slow Memory (
≥
128 Kbytes)
Symbol Parameter Min Max Unit
t
11
Address setup to MAS/ high 25 – ns
t
12
Address hold from MAS/ high 15 – ns
t
13
MAS/ pulse width 25 – ns
t
14
MCE/ low to data clocked in 160 – ns
t
15
Address valid to data clocked in 205 – ns
t
16
MOE/ low to data clocked in 100 – ns
t
17
Data hold from address, MOE/, MCE/ change 0 – ns
t
18
Address out from MOE/, MCE/ high 50 – ns
t
19
Data setup to CLK high 5 – ns
CLK
t
12
MAD/
(Addr driven by
(Driven by LSI53C876)
MAS1/
(Driven by LSI53C876)
MAS0/
(Driven by LSI53C876)
MCE/
(Driven by LSI53C876)
MWE/
(Driven by LSI53C876)
MOE/
High Order
Address
Middle
Address
Order
Address
Low
Valid Read Data
t
11
t
13
t
15
t
14
t
16
t
18
t
17
LSI53C876- Data driven
by Memory)
Order
t
19